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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">PMCFGR, Performance Monitors Configuration Register</h1><p>The PMCFGR characteristics are:</p><h2>Purpose</h2>
        <p>Contains PMU-specific configuration data.</p>
      <h2>Configuration</h2><p>This register is present only when FEAT_PMUv3_EXT is implemented. Otherwise, direct accesses to PMCFGR are <span class="arm-defined-word">RES0</span>.</p>
        <p>PMCFGR is in the Core power domain.</p>
      <h2>Attributes</h2>
        <p>PMCFGR is a:</p>

      
        <ul>
<li>64-bit register when FEAT_PMUv3_EXT64 is implemented
</li><li>32-bit register otherwise
</li></ul>
      <p>This  register is part of the <a href="pmu.html">PMU</a> block.</p><h2>Field descriptions</h2><h3>When FEAT_PMUv3_EXT64 is implemented:</h3><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_0-63_32">RES0</a></td></tr><tr class="firstrow"><td class="lr" colspan="4"><a href="#fieldset_0-31_28-1">NCG</a></td><td class="lr" colspan="5"><a href="#fieldset_0-27_23">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-22_22">SS</a></td><td class="lr" colspan="1"><a href="#fieldset_0-21_21">FZO</a></td><td class="lr" colspan="1"><a href="#fieldset_0-20_20">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-19_19">UEN</a></td><td class="lr" colspan="1"><a href="#fieldset_0-18_18">WT</a></td><td class="lr" colspan="1"><a href="#fieldset_0-17_17">NA</a></td><td class="lr" colspan="1"><a href="#fieldset_0-16_16">EX</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_15">CCD</a></td><td class="lr" colspan="1"><a href="#fieldset_0-14_14">CC</a></td><td class="lr" colspan="6"><a href="#fieldset_0-13_8">SIZE</a></td><td class="lr" colspan="8"><a href="#fieldset_0-7_0">N</a></td></tr></tbody></table><h4 id="fieldset_0-63_32">Bits [63:32]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-31_28-1">NCG, bits [31:28]<span class="condition"><br/>When FEAT_PMUv3_ICNTR is implemented:
                        </span></h4><div class="field">
      <p>Counter Groups. Defines the number of counter groups implemented, minus one.</p>
    
      <p>Reads as <span class="binarynumber">0b0001</span>.</p>
    <p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_0-31_28-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field"><p>Defines the number of counter groups implemented, minus one.</p>
<p>This field reads-as-zero.</p>
      <p>Reads as <span class="binarynumber">0b0000</span>.</p>
    <p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_0-27_23">Bits [27:23]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-22_22">SS, bit [22]</h4><div class="field">
      <p>Snapshot supported.</p>
    <table class="valuetable"><tr><th>SS</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Snapshot mechanism not supported. The locations <span class="hexnumber">0x600</span>-<span class="hexnumber">0x7FC</span> and <span class="hexnumber">0xE30</span>-<span class="hexnumber">0xE3C</span> are <span class="arm-defined-word">IMPLEMENTATION DEFINED</span>.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td><p>Snapshot mechanism supported.</p>
<p>If <span class="xref">FEAT_PMUv3_SS</span> is implemented, then the following registers are implemented:</p>
<ul>
<li>
<p>PMU.PMEVCNTSVR&lt;n&gt;_EL1.</p>

</li><li>
<p>PMU.PMCCNTSVR_EL1.</p>

</li><li>
<p>If <span class="xref">FEAT_PMUv3_ICNTR</span> is implemented, PMU.PMICNTSVR_EL1.</p>

</li><li>
<p>PMU.PMSSCR_EL1.</p>

</li></ul>
<p>Otherwise, locations <span class="hexnumber">0x600</span>-<span class="hexnumber">0x7FC</span> and <span class="hexnumber">0xE30</span>-<span class="hexnumber">0xE3C</span> contain <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> snapshot registers.</p></td></tr></table><p><span class="xref">FEAT_PMUv3_SS</span> implements the functionality identified by the value 1.</p>
<p>If <span class="xref">FEAT_PMUv3_SS</span> is not implemented, a PMU might include an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> snapshot mechanism, including one using the <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> registers <span class="hexnumber">0x600</span>-<span class="hexnumber">0x7FC</span> and <span class="hexnumber">0xE30</span>-<span class="hexnumber">0xE3C</span>.</p>
<p>This field has an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> value.</p><p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_0-21_21">FZO, bit [21]</h4><div class="field">
      <p>Freeze-on-overflow supported. Defined values are:</p>
    <table class="valuetable"><tr><th>FZO</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Freeze-on-overflow mechanism is not supported. PMU.PMCR_EL0.FZO is <span class="arm-defined-word">RES0</span>.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Freeze-on-overflow mechanism is supported. PMU.PMCR_EL0.FZO is RW.</p>
        </td></tr></table><p><span class="xref">FEAT_PMUv3p7</span> implements the functionality added by the value <span class="binarynumber">0b1</span>.</p>
<p>From Armv8.7, if <span class="xref">FEAT_PMUv3</span> is implemented, the only permitted value is <span class="binarynumber">0b1</span>.</p></div><h4 id="fieldset_0-20_20">Bit [20]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-19_19">UEN, bit [19]</h4><div class="field">
      <p>User-mode Enable Register supported. <a href="AArch64-pmuserenr_el0.html">PMUSERENR_EL0</a> is not visible in the external debug interface, so this bit is RAZ.</p>
    
      <p>Reads as <span class="binarynumber">0b0</span>.</p>
    <p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_0-18_18">WT, bit [18]</h4><div class="field">
      <p>This feature is not supported, so this bit is RAZ.</p>
    
      <p>Reads as <span class="binarynumber">0b0</span>.</p>
    <p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_0-17_17">NA, bit [17]</h4><div class="field">
      <p>This feature is not supported, so this bit is RAZ.</p>
    
      <p>Reads as <span class="binarynumber">0b0</span>.</p>
    <p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_0-16_16">EX, bit [16]</h4><div class="field">
      <p>Export supported. Value is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span>.</p>
    <table class="valuetable"><tr><th>EX</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>PMU.PMCR_EL0.X is <span class="arm-defined-word">RES0</span>.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>PMU.PMCR_EL0.X is read/write.</p>
        </td></tr></table>
      <p>This field has an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> value.</p>
    <p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_0-15_15">CCD, bit [15]</h4><div class="field"><p>Cycle counter has prescale.</p>
<p>This is <span class="arm-defined-word">RES1</span> if AArch32 is supported, and RAZ otherwise.</p><table class="valuetable"><tr><th>CCD</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>PMU.PMCR_EL0.D is <span class="arm-defined-word">RES0</span>.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>PMU.PMCR_EL0.D is read/write.</p>
        </td></tr></table></div><h4 id="fieldset_0-14_14">CC, bit [14]</h4><div class="field">
      <p>Dedicated cycle counter (counter 31) supported.</p>
    
      <p>Reads as <span class="binarynumber">0b1</span>.</p>
    <p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_0-13_8">SIZE, bits [13:8]</h4><div class="field"><p>Size of counters, minus one. This field defines the size of the largest counter implemented by the Performance Monitors Unit.</p>
<p>From Armv8, the largest counter is 64-bits, so the value of this field is <span class="binarynumber">0b111111</span>.</p>
<p>This field is used by software to determine the spacing of the counters in the memory-map. From Armv8, the counters are a doubleword-aligned addresses.</p>
      <p>Reads as <span class="binarynumber">0b111111</span>.</p>
    <p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_0-7_0">N, bits [7:0]</h4><div class="field">
      <p>Number of counters, minus one.</p>
    <table class="valuetable"><tr><th>N</th><th>Meaning</th></tr><tr><td class="bitfield">0x00</td><td>
          <p>Only PMU.PMCCNTR_EL0 implemented.</p>
        </td></tr><tr><td class="bitfield">0x01..0x20</td><td>
          <p>Number of counters implemented, 2 to 33, minus one.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>The count includes:</p>
<ul>
<li>
<p>The cycle counter, PMU.PMCCNTR_EL0.</p>

</li><li>
<p>If <span class="xref">FEAT_PMUv3_ICNTR</span> is implemented, the Instruction Counter, PMU.PMICNTR_EL0.</p>

</li></ul>
<p>For example, if PMCFGR.N == <span class="hexnumber">0x07</span> then:</p>
<ul>
<li>
<p>There are eight counters in total.</p>

</li><li>
<p>If <span class="xref">FEAT_PMUv3_ICNTR</span> is not implemented, this comprises 7 event counters and the cycle counter.</p>

</li><li>
<p>If <span class="xref">FEAT_PMUv3_ICNTR</span> is implemented, this comprises 6 event counters, the cycle counter, and the instruction counter.</p>

</li></ul>
<p>This field has an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> value.</p><p>Access to this field is <span class="access_level">RO</span>.</p></div><h3>Otherwise:</h3><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="4"><a href="#fieldset_1-31_28-1">NCG</a></td><td class="lr" colspan="5"><a href="#fieldset_1-27_23">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_1-22_22">SS</a></td><td class="lr" colspan="1"><a href="#fieldset_1-21_21">FZO</a></td><td class="lr" colspan="1"><a href="#fieldset_1-20_20">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_1-19_19">UEN</a></td><td class="lr" colspan="1"><a href="#fieldset_1-18_18">WT</a></td><td class="lr" colspan="1"><a href="#fieldset_1-17_17">NA</a></td><td class="lr" colspan="1"><a href="#fieldset_1-16_16">EX</a></td><td class="lr" colspan="1"><a href="#fieldset_1-15_15">CCD</a></td><td class="lr" colspan="1"><a href="#fieldset_1-14_14">CC</a></td><td class="lr" colspan="6"><a href="#fieldset_1-13_8">SIZE</a></td><td class="lr" colspan="8"><a href="#fieldset_1-7_0">N</a></td></tr></tbody></table><h4 id="fieldset_1-31_28-1">NCG, bits [31:28]<span class="condition"><br/>When FEAT_PMUv3_ICNTR is implemented:
                        </span></h4><div class="field">
      <p>Counter Groups. Defines the number of counter groups implemented, minus one.</p>
    
      <p>Reads as <span class="binarynumber">0b0001</span>.</p>
    <p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_1-31_28-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field"><p>Defines the number of counter groups implemented, minus one.</p>
<p>This field reads-as-zero.</p>
      <p>Reads as <span class="binarynumber">0b0000</span>.</p>
    <p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_1-27_23">Bits [27:23]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_1-22_22">SS, bit [22]</h4><div class="field">
      <p>Snapshot supported.</p>
    <table class="valuetable"><tr><th>SS</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Snapshot mechanism not supported. The locations <span class="hexnumber">0x600</span>-<span class="hexnumber">0x7FC</span> and <span class="hexnumber">0xE30</span>-<span class="hexnumber">0xE3C</span> are <span class="arm-defined-word">IMPLEMENTATION DEFINED</span>.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td><p>Snapshot mechanism supported.</p>
<p>If <span class="xref">FEAT_PMUv3_SS</span> is implemented, then the following registers are implemented:</p>
<ul>
<li>
<p>PMU.PMEVCNTSVR&lt;n&gt;_EL1.</p>

</li><li>
<p>PMU.PMCCNTSVR_EL1.</p>

</li><li>
<p>If <span class="xref">FEAT_PMUv3_ICNTR</span> is implemented, PMU.PMICNTSVR_EL1.</p>

</li><li>
<p>PMU.PMSSCR_EL1.</p>

</li></ul>
<p>Otherwise, locations <span class="hexnumber">0x600</span>-<span class="hexnumber">0x7FC</span> and <span class="hexnumber">0xE30</span>-<span class="hexnumber">0xE3C</span> contain <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> snapshot registers.</p></td></tr></table><p><span class="xref">FEAT_PMUv3_SS</span> implements the functionality identified by the value 1.</p>
<p>If <span class="xref">FEAT_PMUv3_SS</span> is not implemented, a PMU might include an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> snapshot mechanism, including one using the <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> registers <span class="hexnumber">0x600</span>-<span class="hexnumber">0x7FC</span> and <span class="hexnumber">0xE30</span>-<span class="hexnumber">0xE3C</span>.</p>
<p>This field has an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> value.</p><p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_1-21_21">FZO, bit [21]</h4><div class="field">
      <p>Freeze-on-overflow supported. Defined values are:</p>
    <table class="valuetable"><tr><th>FZO</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Freeze-on-overflow mechanism is not supported. PMU.PMCR_EL0.FZO is <span class="arm-defined-word">RES0</span>.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Freeze-on-overflow mechanism is supported. PMU.PMCR_EL0.FZO is RW.</p>
        </td></tr></table><p><span class="xref">FEAT_PMUv3p7</span> implements the functionality added by the value <span class="binarynumber">0b1</span>.</p>
<p>From Armv8.7, if <span class="xref">FEAT_PMUv3</span> is implemented, the only permitted value is <span class="binarynumber">0b1</span>.</p></div><h4 id="fieldset_1-20_20">Bit [20]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_1-19_19">UEN, bit [19]</h4><div class="field">
      <p>User-mode Enable Register supported. <a href="AArch64-pmuserenr_el0.html">PMUSERENR_EL0</a> is not visible in the external debug interface, so this bit is RAZ.</p>
    
      <p>Reads as <span class="binarynumber">0b0</span>.</p>
    <p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_1-18_18">WT, bit [18]</h4><div class="field">
      <p>This feature is not supported, so this bit is RAZ.</p>
    
      <p>Reads as <span class="binarynumber">0b0</span>.</p>
    <p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_1-17_17">NA, bit [17]</h4><div class="field">
      <p>This feature is not supported, so this bit is RAZ.</p>
    
      <p>Reads as <span class="binarynumber">0b0</span>.</p>
    <p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_1-16_16">EX, bit [16]</h4><div class="field">
      <p>Export supported. Value is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span>.</p>
    <table class="valuetable"><tr><th>EX</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>PMU.PMCR_EL0.X is <span class="arm-defined-word">RES0</span>.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>PMU.PMCR_EL0.X is read/write.</p>
        </td></tr></table>
      <p>This field has an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> value.</p>
    <p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_1-15_15">CCD, bit [15]</h4><div class="field"><p>Cycle counter has prescale.</p>
<p>This is <span class="arm-defined-word">RES1</span> if AArch32 is supported, and RAZ otherwise.</p><table class="valuetable"><tr><th>CCD</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>PMU.PMCR_EL0.D is <span class="arm-defined-word">RES0</span>.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>PMU.PMCR_EL0.D is read/write.</p>
        </td></tr></table></div><h4 id="fieldset_1-14_14">CC, bit [14]</h4><div class="field">
      <p>Dedicated cycle counter (counter 31) supported.</p>
    
      <p>Reads as <span class="binarynumber">0b1</span>.</p>
    <p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_1-13_8">SIZE, bits [13:8]</h4><div class="field"><p>Size of counters, minus one. This field defines the size of the largest counter implemented by the Performance Monitors Unit.</p>
<p>From Armv8, the largest counter is 64-bits, so the value of this field is <span class="binarynumber">0b111111</span>.</p>
<p>This field is used by software to determine the spacing of the counters in the memory-map. From Armv8, the counters are a doubleword-aligned addresses.</p>
      <p>Reads as <span class="binarynumber">0b111111</span>.</p>
    <p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_1-7_0">N, bits [7:0]</h4><div class="field">
      <p>Number of counters, minus one.</p>
    <table class="valuetable"><tr><th>N</th><th>Meaning</th></tr><tr><td class="bitfield">0x00</td><td>
          <p>Only PMU.PMCCNTR_EL0 implemented.</p>
        </td></tr><tr><td class="bitfield">0x01..0x20</td><td>
          <p>Number of counters implemented, 2 to 33, minus one.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>The count includes:</p>
<ul>
<li>
<p>The cycle counter, PMU.PMCCNTR_EL0.</p>

</li><li>
<p>If <span class="xref">FEAT_PMUv3_ICNTR</span> is implemented, the Instruction Counter, PMU.PMICNTR_EL0.</p>

</li></ul>
<p>For example, if PMCFGR.N == <span class="hexnumber">0x07</span> then:</p>
<ul>
<li>
<p>There are eight counters in total.</p>

</li><li>
<p>If <span class="xref">FEAT_PMUv3_ICNTR</span> is not implemented, this comprises 7 event counters and the cycle counter.</p>

</li><li>
<p>If <span class="xref">FEAT_PMUv3_ICNTR</span> is implemented, this comprises 6 event counters, the cycle counter, and the instruction counter.</p>

</li></ul>
<p>This field has an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> value.</p><p>Access to this field is <span class="access_level">RO</span>.</p></div><div class="access_mechanisms"><h2>Accessing PMCFGR</h2>
        <div class="note"><span class="note-header">Note</span><p>AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.</p></div>
      <p>Accesses to this register use the following encodings:</p><h4 class="assembler"><span class="condition">
When FEAT_PMUv3_EXT64 is implemented
        </span><br/>[63:0] Accessible at offset 0xE00 from PMU</h4><ul><li>When DoubleLockStatus(), or !IsCorePowered(), or OSLockStatus() or !AllowExternalPMUAccess(), accesses to this register generate an error response.
          </li><li>Otherwise, accesses to this register are <span class="access_level">RO</span>.
          </li></ul><table class="access_instructions"><tr/><tr/></table><h4 class="assembler"><span class="condition">
When FEAT_PMUv3_EXT32 is implemented
        </span><br/>[31:0] Accessible at offset 0xE00 from PMU</h4><ul><li>When DoubleLockStatus(), or !IsCorePowered(), or OSLockStatus() or !AllowExternalPMUAccess(), accesses to this register generate an error response.
          </li><li>Otherwise, accesses to this register are <span class="access_level">RO</span>.
          </li></ul><table class="access_instructions"><tr/><tr/></table></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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